Inside the IOActive Silicon Lab: Interpreting Images

By Andrew Zonenberg @azonenberg

In the post “Reading
CMOS layout,” we discussed understanding CMOS layout in order to reverse-engineer
photographs of a circuit to a transistor-level schematic. This was all well and
good, but I glossed over an important (and often overlooked) part of the
process: using the photos to observe and understand the circuit’s actual

Optical Microscopy